Generally, programmable logic devices may be customized by a user (e.g., an engineer or a logic designer) to implement a desired logic design. By incorporating such devices in multi-die packages, programmable logic devices can be integrated with additional dies providing other logical functions.
However, the increased complexity in programmable logic devices may result in manufacturing defects. Such defects may decrease manufacturing yields and affect the functionality of a device as well as device performance. For example, yield loss may occur when assembling multi-die packages as defects may arise in interconnects between dies. Delay penalty associated with the time for inter-die signals to propagate through the device may also have significant impact on device performance.